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M24512
512 Kbit Serial IC Bus EEPROM
s
Two Wire I2C Serial Interface Supports 400 kHz Protocol Single Supply Voltage: - 4.5V to 5.5V for M24512 - 2.5V to 5.5V for M24512-W - 1.8V to 3.6V for M24512-S
s
8 1
PDIP8 (BN) 0.25 mm frame
s s s s s s s s
Write Control Input BYTE and PAGE WRITE (up to 128 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behavior More than 100,000 Erase/Write Cycles More than 40 Year Data Retention
8
LGA
1
SO8 (MW) 200 mil width LGA8 (LA)
DESCRIPTION These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organised as 64Kx8 bits, and operate down to 2.5 V (for the -W version), and down to 1.8 V (for the -S version). These devices are compatible with the I2C memory protocol. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition.
Figure 1. Logic Diagram
VCC
3 E0-E2 SDA M24512
Table 1. Signal Names
E0, E1, E2 SDA SCL WC VCC VSS Chip Enable Serial Data Serial Clock Write Control Supply Voltage Ground
SCL WC
VSS
AI02275
June 2002
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M24512
Figure 2A. DIP Connections Figure 2C. SO8 Connections
M24512 E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI02276
M24512 VCC WC SCL SDA E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI04035
VCC WC SCL SDA
Figure 2B. LGA Connections
M24512 E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI03791
VCC WC SCL SDA
Table 2. Absolute Maximum Ratings 1
Symbol TA TSTG TLEAD VIO VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering Input or Output range Supply Voltage Electrostatic Discharge Voltage (Human Body model) 3 PDIP: 10 seconds SO: 20 seconds (max) 2 Value -40 to 125 -65 to 150 260 235 -0.6 to 6.5 -0.3 to 6.5 4000 Unit C C C V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. IPC/JEDEC J-STD-020A 3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
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M24512
The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and RW bit (as described in Table 3), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. Power On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. The internal reset is held active until VCC has reached the POR threshold value, and all operations are disabled - the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid V CC must be applied before applying any logic signal. SIGNAL DESCRIPTION Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to V CC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. Serial Data (SDA) This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). Chip Enable (E0, E1, E2) These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to V CC or VSS, to establish the Device Select Code. When unconnected, the Chip Enable (E2, E1, E0) signals are internally read as VIL (see Tables 7 and 8). Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and Write operations are allowed. When Write Control (WC) is driven High, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged.
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC 20 Maximum RP value (k) 16 RL 12 8 4 0 10 100 CBUS (pF)
AI01665
RL
SDA MASTER fc = 100kHz fc = 400kHz SCL CBUS
CBUS 1000
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M24512
Figure 4. I2C Bus Protocol
SCL
SDA SDA Input SDA Change
START Condition
STOP Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP Condition
AI00792B
DEVICE OPERATION The device supports the I2C protocol. This is summarized in Figure 4. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24512 device is always a slave in all communication. Start Condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given.
Stop Condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle. Acknowledge Bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits.
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M24512
Table 3. Device Select Code 1
Device Type Identifier b7 Device Select Code 1 b6 0 b5 1 b4 0 Chip Enable Address b3 E2 b2 E1 b1 E0 RW b0 RW
Note: 1. The most significant bit, b7, is sent first.
Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low. Memory Addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 3 (on Serial Data (SDA), most significant bit first). The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable "Address" (E2, E1, E0). To address the memory array, the 4bit Device Type Identifier is 1010b. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is received on Serial Data (SDA), the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Standby mode.
Table 4. Most Significant Byte
b15 b14 b13 b12 b11 b10 b9 b8
Table 5. Least Significant Byte
b7 b6 b5 b4 b3 b2 b1 b0
Write Operations Following a Start condition the bus master sends a Device Select Code with the RW bit reset to 0. The device acknowledges this, as shown in Figure 6, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if Write Control (WC) is driven High. Any Write instruction with Write Control (WC) driven High (during a period of time from the Start condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 5. Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 4) is sent first, followed by the Least Significant Byte (Table 5). Bits b15 to b0 form the address of the byte in memory. When the bus master generates a Stop condition immediately after the Ack bit (in the "10 th bit" time slot), either at the end of a Byte Write or a Page Write, the internal memory Write cycle is triggered.
Table 6. Operating Modes
Mode Current Address Read Random Address Read 1 Sequential Read Byte Write Page Write
Note: 1. X = VIH or VIL.
RW bit 1 0
WC 1 X X
Bytes 1 1
Initial Sequence START, Device Select, RW = 1 START, Device Select, RW = 0, Address reSTART, Device Select, RW = 1
X X VIL VIL 1 1
1 0 0
Similar to Current or Random Address Read START, Device Select, RW = 0
128
START, Device Select, RW = 0
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M24512
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
WC ACK BYTE WRITE DEV SEL ACK ACK NO ACK DATA IN
BYTE ADDR R/W
BYTE ADDR
WC ACK PAGE WRITE DEV SEL ACK ACK NO ACK DATA IN 1 DATA IN 2
START
BYTE ADDR R/W
BYTE ADDR
WC (cont'd) NO ACK PAGE WRITE (cont'd) NO ACK
START
DATA IN N
STOP
STOP
AI01120C
A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. Byte Write After the Device Select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven High, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Writeprotected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 6. Page Write The Page Write mode allows up to 128 bytes to be written in a single Write cycle, provided that they are all located in the same 'row' in the memory: that is, the most significant memory address bits
(b15-b7) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as `roll-over' occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 128 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If Write Control (WC) is High, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (the 7 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition. Minimizing System Delays by Polling On ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory
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M24512
Figure 6. Write Mode Sequences with WC=0 (data write enabled)
WC ACK BYTE WRITE START DEV SEL R/W ACK ACK DATA IN STOP ACK ACK DATA IN 1 ACK DATA IN 2 BYTE ADDR R/W BYTE ADDR ACK DATA IN N STOP ACK
BYTE ADDR
BYTE ADDR
WC ACK PAGE WRITE START WC (cont'd) ACK PAGE WRITE (cont'd) DEV SEL
AI01106B
cells. The maximum Write time (tw) is shown in Table 9, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 7, is: - Initial condition: a Write cycle is in progress. - Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction). - Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).
Read Operations Read operations are performed independently of the state of the Write Control (WC) signal. Random Address Read A dummy Write is performed to load the address into the address counter (as shown in Figure 8) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. Current Address Read The device has an internal address counter which is incremented each time a byte is read. For the Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the RW bit set to 1. The device acknowledges this, and outputs the byte
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M24512
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle in Progress
START Condition DEVICE SELECT with RW = 0
NO First byte of instruction with RW = 0 already decoded by the device
ACK Returned YES
NO
Next Operation is Addressing the Memory
YES
ReSTART
Send Address and Receive ACK
STOP
NO
START Condition
YES
DATA for the WRITE Operation
DEVICE SELECT with RW = 1
Continue the WRITE Operation
Continue the Random READ Operation
AI01847C
addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 8, without acknowledging the byte. Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 8. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address
counter `rolls-over', and the device continues to output data from memory address 00h. Acknowledge in Read Mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Stand-by mode.
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M24512
Figure 8. Read Mode Sequences
ACK CURRENT ADDRESS READ START DEV SEL R/W NO ACK DATA OUT STOP ACK
ACK RANDOM ADDRESS READ START DEV SEL * R/W
ACK DEV SEL * START
ACK
NO ACK DATA OUT STOP ACK
BYTE ADDR
BYTE ADDR
R/W
ACK SEQUENTIAL CURRENT READ START DEV SEL R/W
ACK
ACK
NO ACK
DATA OUT 1
DATA OUT N STOP
ACK SEQUENTIAL RANDOM READ START DEV SEL *
ACK
ACK DEV SEL * START
ACK
BYTE ADDR R/W
BYTE ADDR
DATA OUT 1 R/W
ACK
NO ACK
DATA OUT N STOP
AI01105C
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 4 bytes) must be identical.
st
th
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M24512
Table 7. DC Characteristics (TA = 0 to 70 C or -40 to 85 C; (TA = 0 to 70 C or -20 to 85 C;
Symbol ILI ILI ILO Parameter Input Leakage Current (SCL, SDA) Input Leakage Current (E2, E1, E0, WC) Output Leakage Current
VCC = 4.5 to 5.5 V or 2.5 to 5.5 V) VCC = 1.8 to 3.6 V)
Test Condition VIN = VSS or VCC VIN = VSS VOUT = VSS or VCC, SDA in Hi-Z VCC=5V, fc=400kHz (rise/fall time < 30ns) Min. Max. 2 5 2 2 1 0.81 10 2 11 - 0.3 0.7VCC IOL = 3 mA, VCC = 5 V 0.3VCC VCC+1 0.4 0.4 0.21 Unit A A A mA mA mA A A A V V V V V
ICC
Supply Current
-W series: -S series:
VCC =2.5V, fc=400kHz (rise/fall time < 30ns) VCC =1.8V, fc=400kHz (rise/fall time < 30ns) VIN = VSS or VCC , VCC = 5 V
ICC1
Supply Current (Stand-by)
-W series: -S series:
VIN = VSS or VCC , VCC = 2.5 V VIN = VSS or VCC , VCC = 1.8 V
VIL VIH
Input Low Voltage Input High Voltage
VOL
Output Low Voltage
-W series: -S series:
IOL = 2.1 mA, VCC = 2.5 V IOL = 0.15 mA, VCC = 1.8 V
Note: 1. This is preliminary data.
Table 8. Input Parameters1 (TA = 25 C, f = 400 kHz)
Symbol CIN CIN ZL ZH tNS Parameter Input Capacitance (SDA) Input Capacitance (other pins) Input Impedance (E2, E1, E0, WC) Input Impedance (E2, E1, E0, WC) Pulse width ignored (Input Filter on SCL and SDA) VIN VIL VIN VIH Single glitch 50 500 200 Test Condition Min. Max. 8 6 300 Unit pF pF k k ns
Note: 1. Sampled only, not 100% tested.
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M24512
Table 9. AC Characteristics
M24512 Symbol Alt. Parameter VCC=4.5 to 5.5 V VCC=2.5 to 5.5 V VCC=1.8 to 3.6 V TA=0 to 70C or TA=0 to 70C or TA=0 to 70C or Unit -40 to 85C -40 to 85C -20 to 85C4 Min tCH1CH2 tCL1CL2 tDH1DH2
2
Max 300 300
Min
Max 300 300
Min
Max 300 300 ns ns ns ns ns ns ns s s ns ns s 900 ns ns 400 10 kHz ms
tR tF tR tF tSU:STA tHIGH tHD:STA
Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) 20 20 600 600 600 0 1.3 100 600 1.3 200 200
300 300
20 20 600 600 600 0 1.3 100 600 1.3
300 300
20 20 600 600 600 0 1.3 100 600 1.3
300 300
tDL1DL2 2 tCHDX
1
tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV 3 tCLQX fC tW
Note: 1. 2. 3. 4.
tHD:DAT Clock Low to Input Transition tLOW tSU:DAT Clock Pulse Width Low Input Transition to Clock Transition
tSU:STO Clock High to Input High (STOP) tBUF tAA tDH fSCL tWR Input High to Input Low (Bus Free) Clock Low to Data Out Valid Data Out Hold Time After Clock Low Clock Frequency Write Time
900
200 200
900
200 200
400 10
400 10
For a reSTART condition, or following a Write cycle. Sampled only, not 100% tested. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. This is preliminary data.
Table 10. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages 50 ns 0.2VCC to 0.8VCC
Figure 9. AC Measurement Conditions
0.8VCC 0.7VCC 0.3VCC
AI00825
0.2VCC
0.3VCC to 0.7VCC
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M24512
Figure 10. AC Waveforms
tCHCL tCLCH
SCL tDLCL SDA In tCHDX START Condition SDA Input tCLDX SDA tDXCX Change tCHDH tDHDL START STOP Condition Condition
SCL
SDA In tCHDH STOP Condition tW Write Cycle tCHDX START Condition
SCL tCLQV SDA Out Data Valid tCLQX
AI00795C
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M24512
Table 11. Ordering Information Scheme
Example: M24512 -W MW 6 T
Memory Capacity 512 512 Kbit (64K x 8) T
Option Tape and Reel Packing
Operating Voltage blank 4.5 V to 5.5 V W S
1
2.5 V to 5.5 V 1.8 V to 3.6 V
Package BN MW LA PDIP8 (0.25 mm frame) SO8 (200 mil width) LGA8 (Land Grid Array) 5 6
Temperature Range -20 C to 85 C -40 C to 85 C
Note: 1. The -S version (VCC range 1.8 V to 3.6 V) only available in temperature ranges 5.
ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all 1s (FFh). The notation used for the device number is as shown in Table 11. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
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M24512
PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
b2 A2 A1 b e A L
E
c eA eB
D
8
E1
1 PDIP-B
Note: 1. Drawing is not to scale.
PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm Symb. Typ. A A1 A2 b b2 c D E E1 e eA eB L 3.30 2.92 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 7.62 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 - - 4.95 0.56 1.78 0.36 10.16 8.26 7.11 - - 10.92 3.81 0.130 0.115 0.130 0.018 0.060 0.010 0.365 0.310 0.250 0.100 0.300 Min. Max. 5.33 0.015 0.115 0.014 0.045 0.008 0.355 0.300 0.240 - - 0.195 0.022 0.070 0.014 0.400 0.325 0.280 - - 0.430 0.150 Typ. Min. Max. 0.210 inches
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M24512
SO8 wide - 8 lead Plastic Small Outline, 200 mils body width
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
Note: Drawing is not to scale.
SO8 wide - 8 lead Plastic Small Outline, 200 mils body width
mm Symb. Typ. A A1 A2 B C D E e H L N CP 1.27 0.20 0.35 - 5.15 5.20 - 7.70 0.50 0 8 0.10 0.10 Min. Max. 2.03 0.25 1.78 0.45 - 5.35 5.40 - 8.10 0.80 10 0.050 0.008 0.014 - 0.203 0.205 - 0.303 0.020 0 8 0.004 0.004 Typ. Min. Max. 0.080 0.010 0.070 0.018 - 0.211 0.213 - 0.319 0.031 10 inches
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M24512
LGA8 - 8 lead Land Grid Array
CONTACT 1 D D1 T3 E1 E T1 k E2
T2 A A1 A2
E3
ddd
LGA-Z01B
Note: 1. Drawing is not to scale.
LGA8 - 8 lead Land Grid Array
mm Symb. Typ. A A1 A2 D D1 E E1 E2 E3 k T1 T2 T3 ddd 1.040 0.340 0.700 8.000 0.100 5.000 1.270 3.810 0.390 0.100 0.410 0.670 0.970 0.100 Min. 0.940 0.300 0.640 7.900 - 4.900 - - - - - - - - Max. 1.140 0.380 0.760 8.100 - 5.100 - - - - - - - - Typ. 0.0409 0.0134 0.0276 0.3150 0.0039 0.1969 0.0500 0.1500 0.0154 0.0039 0.0161 0.0264 0.0382 0.0039 Min. 0.0370 0.0118 0.0252 0.3110 - 0.1929 - - - - - - - - Max. 0.0449 0.0150 0.0299 0.3189 - 0.2008 - - - - - - - - inches
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M24512
Revision History
Date Rev. Description of Revision Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated LGA8 and SO8(wide) packages added References to PSDIP8 changed to PDIP8, and Package Mechanical data updated LGA8 Package Mechanical data and illustration updated SO16 package removed LGA8 Package given the designator "LA" LGA8 Package mechanical data updated Document becomes Preliminary Data Test conditions for ILI, ILO, ZL and ZH made more precise VIL and VIH values unified. tNS value changed Document becomes Full Datasheet
29-Jan-2001
1.1
10-Apr-2001 16-Jul-2001 02-Oct-2001 13-Dec-2001 12-Jun-2001
1.2 1.3 1.4 1.5 1.6
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M24512
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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